The present invention relates to a method for fabricating an electronic device and, more particularly, to a wiring forming technique.
In recent years, reduction in size, higher packing density, and higher speed of a semiconductor integrated circuit are in demand and, accordingly, reduction in wiring resistance and wiring capacitance and improvement in reliability of a semiconductor integrated circuit are necessary. To realize reduction in wiring resistance and improvement in reliability of a semiconductor integrated circuit, copper wiring having specific resistance lower than that of a conventional aluminum alloy and having high reliability is used in practice.
To reduce wiring capacitance, an insulating film having a low dielectric constant (hereinbelow, called a low dielectric constant film), for example, a silicon oxide film containing carbon is started to be used in place of a conventional silicon oxide film. The lower dielectric constant of the low dielectric constant film is realized by reducing density of a silicon oxide film by making carbon in the form of an alkyl group or phenyl group of large volume exist in the silicon oxide film. Another method for lowering the dielectric constant by reducing density of the silicon oxide film by forming small pores in the silicon oxide film is also proposed.
To realize reduction in wiring resistance, reduction in wiring capacitance, and improvement in reliability of a semiconductor integrated circuit, a wiring technique obtained by combining copper wiring and a low dielectric constant film is increasingly becoming necessary.
As a first prior art, a damascene method generally used for copper wiring will be described.
A copper wiring forming method using dual damascene will be described as an example (refer to, for example, Japanese Patent Laid-open No. 2000-323571).
First, a wiring trench and a connection hole whose bottom reaches the top face of a lower layer wiring are formed in an interlayer insulating film formed on the lower layer wiring made by a copper film. After that and before a barrier metal film is formed on the wiring trench and the side wall and the bottom of the connection hole, sputter etching using argon gas is performed on the bottom of the connection hole, thereby removing a natural oxide film formed on the surface of the lower layer wiring exposed from the bottom of the connection hole. At the time of sputter etching, the surface of the lower layer wiring is sputtered, so that copper sputtered is deposited on the side wall of the connection hole. A barrier metal film is formed on the wiring trench and the side wall and bottom of the connection hole. After that, a copper film is filled in the wiring trench and the connection hole in which the barrier metal film is formed, thereby forming an upper layer wiring.
Since the copper deposited on the side wall of the connection hole by the sputter etching using argon gas is in direct contact with the interlayer insulating film, the deposit of copper moves into the interlayer insulating film in a following process such as a heating process, and it causes a problem such as a leak between wirings. Simultaneously, the copper of the lower layer wiring is diffused into the interlayer insulating film by using the deposit as a diffusion path, so that a problem such as stress migration that a void is generated in the lower layer wiring occurs.
Meanwhile, in a future device, use of a low dielectric constant film as the interlayer insulating film is in increasing demand. When the density of the interlayer insulating film accordingly becomes lower, diffusion of copper deposited on the side wall of the connection hole and copper of the lower layer wiring using the deposit as a diffusion path into the interlayer insulating film appears more conspicuously.
Further, the copper deposited on the side wall of the interlayer insulating film is not uniform, so that morphology is bad and rough. Consequently, a barrier metal film formed on the deposit of copper on the side wall of the interlayer insulating film is partially thinner as compared with the case where the barrier metal film is directly formed on the side wall of the interlayer insulating film. Therefore, as a semiconductor integrated circuit is becoming finer in the future, the thickness of the barrier metal film formed on the side wall of the interlayer insulating film is reduced, and the barrier metal film formed on the copper deposit on the side wall of the interlayer insulating film cannot assure sufficient film thickness. Moreover, a discontinuous part is created in the barrier metal film. As a result, an interface state having excellent adhesion between the barrier metal film and the copper film formed on the barrier metal film cannot be assured and a void nucleus forming site is created in the interface between the barrier metal film and the copper film. It causes poor reliability of a semiconductor integrated circuit, in particular, a problem such as electro-migration or stress migration.
When the barrier metal film has a thinned portion or a discontinued portion, a problem may occur after formation of wiring. Concretely, a trouble occurs due to heat generated in a heat treatment process in the upper wiring forming process performed after formation of the barrier metal film or heat generated at the time of a high-temperature storage test after completion of the device. For example, when heat is conducted to the wiring, the copper in the connection hole passes through the thin portion and the discontinuous portion in the barrier metal film and is diffused into the interlayer insulting film. As a result, a trouble related to stress migration such as generation of a leak current to the interlayer insulating film and formation of a void in the copper film of the connection hole occurs.
Therefore, as a countermeasure against the problems occurring in the first prior art, a second prior art has been examined.
To be specific, a method for reducing and removing a natural oxide film of copper formed on the bottom of a connection hole by performing a plasma process using hydrogen (H2) gas as a reducing gas in place of sputter etching using argon gas in the first prior art has been examined. According to the method, since hydrogen is a light element, physical sputter etching is not carried out. Therefore, the copper of the lower layer wiring is not spread and deposited on the side wall of the connection hole.
As another countermeasure against the problems occurring in the first prior art, a third prior art has been examined.
To be specific, a method for forming a barrier metal film without performing sputter etching using argon gas to remove a natural oxide film formed on the surface of a lower layer wiring which is a copper film prior to formation of the barrier metal film, after that, removing the barrier metal film formed on the bottom of a connection hole and, further, removing the natural oxide film by sputter etching is proposed.
A method for fabricating an electronic device according to the third prior art will be described hereinbelow with reference to FIGS. 5A to 5C and FIGS. 6A and 6B.
As shown in FIG. 5A, a first insulating film 101 is formed on a substrate 100 and, by using damascene, a lower layer wiring 102 is formed in the first insulating film 101. Although not shown, the lower layer wiring 102 is obtained by stacking a barrier metal film 102a which is a tantalum nitride film and copper 102b in order. On the first insulating film 101 and the lower layer wiring 102, a barrier insulating film 103 for protecting the lower layer wiring 102, a second insulating film 104 which is a silicon oxide film, and a third insulating film 105 which is a silicon nitride film are formed sequentially. After that, by using lithography and dry etching technique, an opening 106 as a part of a connection hole is formed in the third insulating film 105.
As shown in FIG. 5B, a fourth insulating film 107 which is a silicon oxide film is formed on the third insulating film 105 including the opening 106. In such a manner, an interlayer insulating film 108 is formed by the second, third, and fourth insulating films 104, 105, and 107. Next, by using lithography and dry etching technique, a wiring trench 109 is formed in the fourth insulating film 107 so that the opening 106 exists in its bottom. Further, by using the third insulating film 105 as a mask, dry etching is performed successively on the second insulating film 104 and the barrier insulating film 103 to form a through hole which is communicated with the opening 106 and exposes the surface of the lower wiring 102 in the second insulating film 104 and the barrier insulating film 103 (hereinbelow, the through hole and the opening 106 will be called a connection hole 110).
As shown in FIG. 5C, a first barrier metal film 111 made of, for example, a tantalum nitride film is formed on the fourth insulating film 107 and each bottom and side wall of the wiring trench 109 and the connection hole 110 by sputtering. Unlike the first prior art, sputter etching is not performed before the first barrier metal film 111 is formed.
By etching back the first barrier metal film 111 by anisotropic etching, the first barrier metal film 111 formed on the bottom of the connection hole 110 is removed. In this case, the first barrier metal film 111 formed on the fourth insulating film 107 and the bottom of the wiring trench 109 is also removed.
By performing sputter etching using argon gas, a natural oxide film formed on the surface of the lower layer wiring 102 exposed from the bottom of the connection hole 110 is removed. In this case, a part of copper of the lower layer wiring 102 and the like is removed at the time of removing the natural oxide film, and a deposit 112 of copper and the like is made on the first barrier metal film 111 formed on the side walls of the connection hole 110 and the wiring trench 109.
After that, as shown in FIG. 6A, a second barrier metal film 113 which is, for example, a tantalum nitride film is formed by sputtering so as to cover the fourth insulating film 107, the first barrier metal film 111 formed on the side wall of the wiring trench 109, the third insulating film 105, and the first barrier metal film 111 formed on the side wall of the connection hole 110. Then, a copper film 114 as a seed layer used for electroplating is formed on the second barrier metal film 113 by sputtering.
As shown in FIG. 6B, copper is filled in the wiring trench 109 and the connection hole 110 by electroplating. After that, the copper and the second barrier metal film 113 formed on the fourth insulating film 107 are removed by chemical mechanical polishing (CMP) so that the copper filled in the wiring trench 109 and the connection hole 110 remains. In such a manner, an upper layer wiring 115 made of copper and the like is formed in the wiring trench 109, and a wiring plug made of copper and the like is formed in the connection hole 110.
As described above, in the third prior art, the first barrier metal film 111 is formed on each side wall and each bottom of the wiring trench 109 and the connection hole 110. After that, the first barrier metal film 111 formed on the bottom of the connection hole 110 is selectively removed by etch back to expose the surface of the lower layer wiring 102 from the bottom of the connection hole 111. Consequently, the first barrier metal film 111 remains on the side walls of the wiring trench 109 and the connection hole 110. By sputter-etching the bottom of the connection hole 110, the natural oxide film formed on the surface of the lower layer wiring 102 exposed from the bottom of the connection hole 110 can be removed. In this case, copper of the lower layer wiring 102 and the like removed by the sputter etching is deposited on the side wall of the connection hole 110 and the like. However, since the first barrier metal film 111 remains on the side wall of the connection hole 110, the deposit 112 of copper and the like does not come into direct contact with the interlayer insulating film 108. Consequently, copper of the deposit 112 does not move and diffuse into the interlayer insulating film 108.